1. Field of the Invention
The present invention relates to a management apparatus which in order to manage registers in a physical layer apparatus in an Ethernet system of a giga bps level or higher speed, converts external bus interface into management data input/output (MDIO) interface and communicates data between a control base processor and a physical layer apparatus, and a method for converting the interface.
2. Description of the Related Art
In the prior art, in order to manage registers in a physical layer apparatus in an Ethernet system of a giga bps level speed, a control station processor supporting MDIO interface of a direct access method has been used. In addition, in order to manage registers in a physical layer apparatus in an Ethernet system of an over 10 Gbps level speed, a control processor supporting MDIO interface of an indirect access method is used and through an automatic confirmation process, registers in a physical layer apparatus are managed. In most of other gigabit Ethernet systems or the Ethernet physical layers connected to multiport switches, a control station processor supporting MDIO interface of a direct access method is used and through an automatic confirmation process, state registers of the physical layer apparatus are efficiently managed or addresses are assigned.
FIG. 1 is a diagram of the structure of a register management apparatus of a prior art Ethernet physical layer apparatus of a giga bps level or higher speed. FIG. 1 shows that a control station is formed with a processor supporting MDIO interface and a unit for managing Ethernet physical layer apparatus registers is formed only by the processor control station and the Ethernet physical layer apparatus so that the control station processor directly accesses registers in the Ethernet physical layer apparatus.
FIG. 2 is a frame diagram of an MDIO interface signal of a prior art Ethernet physical layer apparatus of a giga bps level or higher speed. A direct access method management signal frame 201 comprises a 32-bit preamble signal, a 2-bit start of frame (ST) signal indicating the start of a frame, a 2-bit operation code (OP) signal indicating the operation purpose of a management signal frame, a 5-bit physical address (PHYAD) signal indicating a predetermined address in a physical layer, a 5-bit register address (REGAD) signal indicating the register address of a corresponding physical layer, a 2-bit turn around (TA) signal, a 16-bit data area, and an Idle signal. An indirect access method management signal frame 202 comprises a 32-bit preamble signal, a 2-bit ST signal indicating the start of a frame, a 2-bit OP signal indicating the operation purpose of a management signal frame, a 5-bit port address (PA) signal which is added by considering expandability of the Ethernet, a 5-bit device address (DA) signal, a 2-bit TA signal, a 16-bit address/data signal, and an idle signal.
The direct access method management signal frame 201 defines 32 bits of the preamble signal as all 1's, the ST signal as ‘01’, and if the purpose is to read, the OP signal as ‘10’, and if the purpose is to write, the OP signal as ‘01’. Then, by using the PHYAD signal and REGAD signal, a corresponding register in the physical layer apparatus is accessed, data is transmitted using an independent data area, and the frame 201 is used in an Ethernet system of a less than gigabit transmission speed.
The indirect access method management signal frame defines 32 bits of the preamble signal as all 1's, the ST signal as ‘00’, and if the purpose is to address, the OP signal as ‘00’, if the purpose is to write, as ‘01’, if the purpose is to read, as ‘11’, and if the purpose is to read and increment, as ‘10’. Then, by using the PA signal, the DA signal, and an address recorded in the address/data area of an address frame, a corresponding register in the physical layer apparatus is accessed. However, since there is no independent data area, immediately after address information is loaded in the address/data area and the address frame is transmitted, data is inserted into the address/data area and a data frame is transmitted. By doing so, data is transmitted and the frame 202 is used in an Ethernet system of a 10 gigabit or higher speed.
FIG. 3 is a timing diagram of a prior art external bus interface signal.
Based on an external bus interface operation clock (EBICLK), the timing diagram of FIG. 3 shows the timings of an address bus signal ADDR(n), a device signal CS for selecting a device to which a corresponding register belongs, a signal R/W* for reading and writing data, an output enable signal OE for a device to which a corresponding register belongs, a signal BLAST to indicate whether or not burst-type transmission of a plurality of addresses is performed, a signal Write Byte Enable (WBE) for controlling to write data in units of bytes, a data bus signal DATA, a signal Par for parity check of communications data, and a signal Err indicating an error of communications data confirmed by the parity check result. In FIG. 3, the frequency of EBICLK can be varied according to a control station processor, and also, the R/W* signal can be allocated to separate signal. In addition, when one address is transmitted in one cycle, BLAST is kept activated until immediately before the communications finishes and then is inactivated. A and B may vary according to a used column of the data bus, and are determined in units of bytes.
In order to manage registers of a physical layer apparatus by using external bus interface instead of MDIO interface, the control station processor should convert the external bus interface into the MDIO interface. The external bus interface comprises a chip select (CS) signal, a clock signal of a 26 MHz˜33 MHz or higher frequency, an address bus, a data bus, and a read not write (R/W*) signal, and transmits data in parallel. The MDIO interface comprises a clock signal of a management data clock (MDC) with a maximum frequency of 2.5 MHz and a bidirectional signal MDIO, and transmits data serially through one signal pin. Accordingly, in order to support both interfaces of different types, having a data processing method difference between parallel data processing and serial data processing, and a processing time difference from different frequencies, the control station processor should consider masking of the data bus and address bus and other problems.
However, though in order to manage registers in a physical layer apparatus of an Ethernet system with a giga bps level or higher speed, the control station processor should support the MDIO interface, but it is practically impossible for all control station processors selected by the characteristic of a system to support the MDIO interface.